1. Field of the Invention
The present invention relates to a multilayered substrate for a semiconductor device, and more particularly, to a multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality of sets of a conductor layer and an insulation layer, i.e., a laminate of alternate conductor and insulation layers, and having a face for mounting semiconductor element thereon and another face for external connection terminals, the face for mounting semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit.
2. Description of the Related Art
A multilayered substrate for a semiconductor device as shown in FIG. 10 is proposed in Japanese Unexamined Patent Publication No. 2000-323613 (corresponding to U.S. Pat. No. 6,418,615). Multilayered substrate body 105 is included in multilayered substrate 100 for a semiconductor device shown in FIG. 10 that is composed by arranging conductor wiring 102 in multiple layers stacked with insulation layers 104 composed of a polyimide resin or a resin such as polyphenylene ether. One side of this multilayered substrate body 105 is a face for mounting semiconductor elements on which is formed semiconductor element pads 120a that are connected to electrode terminals 108 of semiconductor element 106 that is mounted thereon, while the other side of multilayered substrate body 105 is a face for external connection terminals on which is formed external connection terminal pads 124 that are attached to solder balls 122 as external connection terminals. The face for mounting semiconductor devices and the face for external connection terminals of this multilayered substrate body 105 are covered with solder resist 126 with the exception of semiconductor element pads 120a and external connection terminal pads 124.
In this type of multilayered substrate body 105, the conductor wiring 102 and/or pads formed on both sides of each insulation layer 104 (pads 120 for connecting two wiring layers to each other, pads 124 for external connection terminals or pads 120a for electrode terminals of semiconductor element) are electrically connected by vias 128 formed passing through insulation layers 104. These vias 128 are formed in openings 130 which are opened in the side of insulation layer 104 having the face for external connection terminals, and have the bottom formed by the faces of conductor wiring 102 or pads 120 and 120a formed on the side of the same insulation layer 104 having the face for mounting semiconductor elements. Moreover, a metal frame 117 having a prescribed strength can be joined to the periphery of multilayered substrate body 105 in order to improve handling ease, etc. during transport and so forth of multilayered substrate 100 for a semiconductor device.
As shown in FIGS. 11A through 11F, multilayered substrate 100 for a semiconductor device shown in FIG. 10 can be produced by alternately forming conductor wiring and insulation layers from a semiconductor element mounting layer having a face for mounting semiconductor elements in the direction of an external connection terminal attachment layer having a face for external connection terminals.
To begin with, seed layer 142 is formed on one side of a metal sheet in the form of copper sheet 140 (FIG. 11A). This seed layer 142 is composed of chromium (Cr) layer 141a, which is in direct contact with the face of copper sheet 140, and copper (Cu) layer 141b formed on chromium (Cr) layer 141a as shown in FIG. 12, which is an enlarged view of the section indicated with circle A in FIG. 11A.
Semiconductor element pads 120a, to which electrode terminals 108 of semiconductor element 106 are later connected and which are composed of copper, are formed by forming a photoresist pattern (not shown) on seed layer 142 formed on one side of copper sheet 140, exposing seed layer 142 at the sections where semiconductor element pads 120a are formed, and then performing electrolytic plating using seed layer 142, and particularly copper layer 141b, as the power supply layer (FIG. 11B).
Insulation layer 104 is formed by coating a thermosetting resin in the form of a polyimide resin by printing and so forth followed by curing so as to cover semiconductor element pads 120a formed in this manner (FIG. 1C). Continuing, openings 130 for forming vias are formed in insulation layer 104 by laser light such as YAG laser light or carbon dioxide laser light (FIG. 1D).
Seed layer 142′, composed of a chromium (Cr) layer and copper (Cu) layer, is formed over the entire surface of insulation layer 104, including the inner walls of formed openings 130 (FIG. 11E). Next, sections corresponding to vias 128 and conductor wiring 102 (FIG. 10) are formed by electrolytic copper plating using the resist pattern (not shown) formed on seed layer 142′ as a mask, and seed layer 142′ as a power supply layer.
Next, vias 128 and conductor wiring 102 are formed in the surface of insulation layer 104 as shown in FIG. 11F by removing seed layer 142′, except for those sections corresponding to vias 128 and conductor wiring 102, by etching.
Continuing, conductor wiring and insulation layers are sequentially formed from the side of the semiconductor element mounting layer having a face for mounting semiconductor elements in the direction of the external connection terminal attachment layer having a face for external connection terminals by repeating the steps of FIGS. 11C through 11F, thereby allowing the obtaining of intermediate 100a shown in FIG. 13. On one side of multilayered substrate body 105 of the resulting intermediate 100a, copper sheet 140 is joined via seed layer 142 to the face for mounting semiconductor element on which semiconductor mounting pads 120a are formed, and on the other side of multilayered substrate body 105, external connection terminal pads 124 are formed. Copper sheet 140 fulfills the role of a reinforcing sheet of multilayered substrate body 105, and facilitates handling of intermediate 100a during transport and so forth.
Finally, it is necessary to remove copper sheet 140 from intermediate 100a by etching in order to obtain multilayered substrate 100 for a semiconductor device shown in FIG. 10. By forming chromium (Cr) layer 141a, which is not etched by the etching solution of copper sheet 140, as a portion of seed layer 142, the progress of the etching can be inhibited when etching has reached chromium (Cr) layer 141a of seed layer 142 during etching of copper sheet 140, and etching of copper sheet 140 ends at the point the entire surface of chromium (Cr) layer 141a of seed layer 142 is exposed. Next, by removing chromium (Cr) layer 141a and copper (Cu) layer 141b by etching, the surface of semiconductor element pads 120a is exposed, thereby allowing the obtaining of multilayered substrate 100 for a semiconductor device shown in FIG. 10.
Multilayered substrate 100 for a semiconductor device shown in FIG. 10 can be produced so that the face on which semiconductor elements are mounted is as flat as possible and the thickness of the substrate is as thin as possible. However, the inventors of the present invention found that, even if multilayered substrate 100 for a semiconductor device shown in FIG. 10 is reinforced by joining a metal frame 117 on the face for mounting semiconductor elements of multilayered substrate body 105, warping occurs easily caused by a difference in the coefficients of thermal expansion between metal frame 117 and multilayered substrate body 105 composed mainly of a resin, and that warping also occurs easily in intermediate 100a (FIG. 13) during its production process caused by a difference in the coefficients of thermal expansion between copper sheet 140 and multilayered substrate body 105 composed mainly of a resin.
If a thick metal frame 117 is used to prevent the occurrence of this warping, the characteristics of a thin and lightweight multilayered substrate 100 for a semiconductor device are lost.